RTL-Bench

What is RTL-Bench?

RTL-BenchLS evaluates LLMs on RTL design generation and reasoning, containing over 10,000 formally verified Verilog designs. Tasks include specification-to-RTL…

Released

2026-06-08

Evaluates

Chip Design & EDA, Language & Knowledge, Reasoning

Openness

unknown

Importer

Claire Radar

Review status

unreviewed

Reported scores

0

Source provenance

• Original evidence https://arxiv.org/abs/2606.08976

RTL-Bench paper

• Paper https://arxiv.org/abs/2606.08976

Which sources cite RTL-Bench?

• RTL-Bench

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