VeriBugBench

What is VeriBugBench?

VeriBugBench is a framework for constructing Verilog RTL debugging benchmarks using empirically grounded fault construction, LLM-based testbench enhancement…

Released

2026-09-16

Evaluates

Chip Design & EDA, Language & Knowledge, cs.AR

Openness

unknown

Importer

Claire Radar

Review status

ai-name-audit-deferred

Reported scores

0

Source provenance

• Original evidence https://arxiv.org/abs/2609.18022

VeriBugBench paper

• Paper https://arxiv.org/abs/2609.18022

Which sources cite VeriBugBench?

• VeriBugBench

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