HierSVA-B Benchmark

What is HierSVA-B?

HierSVA-B evaluates LLM-generated SystemVerilog assertions for hierarchical hardware formal verification across six quality axes.

Released

2026-06-09

Evaluates

Chip Design & EDA, Language & Knowledge, cs.AR

Openness

unknown

Importer

Claire Radar

Review status

ai-reviewed

Reported scores

0

Source provenance

• Original evidence https://arxiv.org/abs/2606.13706

HierSVA-B paper, code and dataset

• Paper https://arxiv.org/abs/2606.13706
• Code https://github.com/HierSVAAnon/HierSVACodeAndArtifacts
• Dataset https://huggingface.co/datasets/AnonymousHierSVA/HierSVA

Which sources cite HierSVA-B?

• HierSVA-B

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