AssertLLM2 Benchmark

What is AssertLLM2?

Evaluates LLM generation of SystemVerilog assertions from structured design specifications and RTL, across two tasks: bug-prevention and bug-hunting. The…

Released

2026-05-26

Evaluates

Chip Design & EDA, Language & Knowledge, cs.AR

Openness

unknown

Importer

Claire Radar

Review status

unreviewed

Reported scores

0

Source provenance

• Original evidence https://arxiv.org/abs/2605.27472

AssertLLM2 paper

• Paper https://arxiv.org/abs/2605.27472

Which sources cite AssertLLM2?

• AssertLLM2

Related Chip Design & EDA, Language & Knowledge, cs.AR benchmarks

• 5-Dialects-BN
• A Large-Scale Dataset and Benchmark
• AARRI-Bench
• ABC-Bench
• ActiveSciBench
• AdaMem-Bench
• AdvancedMathBench
• AdversaBench